Conventionally, there is a semiconductor device including a cell portion having a JFET and an outer peripheral breakdown proof portion surrounding the cell portion (see JP-2005-340249A1 and JP-2005-340250A1, which correspond to US2005/0258454A1). FIG. 27 is a diagram illustrating a sectional structure of a JFET of this kind of a SiC semiconductor device as related art.
As shown in FIG. 27, the JFET is formed using a semiconductor substrate J6, in which a drift layer J2 made of n−-type SiC, a p−-type SiC layer J3, a buffer layer J4 made of n−-type or p−-type SiC, and an n+-type source layer J5 are formed, in turn, on a n+-type SiC base J1. A trench J7 is formed in the semiconductor substrate J6. The semiconductor substrate J6 includes a channel layer J8 made of n−-type SiC and a top gate layer J9 made of p+-type SiC, which are embedded in the trench J7.
In this configuration, a part of the p+-type SiC layer J3 adjoining the channel layer J8 acts as an embedded gate layer J10. An extension amount of a depletion layer in the channel layer J8 sandwiched between the top gate layer J9 and the embedded gate layer J10 can be controlled by voltage application to the top gate layer J9 and the embedded gate layer J10. Specifically, the top gate layer J9 is electrically connected to a gate wire J12 via a contact hole J11a formed in an interlayer insulation film J11. The embedded gate layer J10 is electrically connected to the gate wire J12 via a trench J13 and a contact hole J11b. The trench J13 penetrates through the n+-type source layer J5 and the buffer layer J4 into the p+-type SiC layer J3. The contact hole J11b is formed in the inter-layer insulation film J11.
A source electrode J14 is connected to the n+-type source layer J5 via a contact hole J11c formed in the inter-layer insulation film J11 and a drain electrode J15 is connected to a rear surface of the n+-type SiC base J1, so that a current flows between a drain and a source when the channel region is formed in the channel layer J8.
According to the above-configured JFET, however, an electrical connection between the embedded gate layer J10 and the gate wire J12 is made via the trench J13, which penetrates through the n+-type source layer J5 and the buffer layer J4 into the p+-type SiC layer J3. In this kind of structure, since the interlayer insulation film J11 and the gate wire J12 are arranged in the trench 13, width of the trench J13 becomes large, and sufficient downsizing cannot be achieved. For this reason, it is desirable to provide a structure that can downsize a contact structure between the embedded gate layer J10 and the gate wire J12.
It should be noted that although the above explanation is directed to the semiconductor device using SiC as its semiconductor material, the same is applicable to a semiconductor device using other semiconductor materials.